The present invention relates generally to a native instruction conversion method and reversion apparatus including an adaptive memory system, and more specifically, it relates to an Adaptive Code Fraction Reduction Method and System Apparatus for Microprocessor System to reduce code fraction, to scale code for packing native instructions at software compilation time, and to adaptively, concurrently prefetch both the mixed PANIs and NIPIs as well as fetch purely native instructions at runtime.
In order to reduce code fraction, the Adaptive Code Fraction Reduction Method generally packs segments of native instructions between two instructions that cause fraction of code including branch and branch target instructions, the so-called basic blocks as done in prior arts. In addition, the invention permits packing already packed instructions, such as PANIs, with NIPIs and/or other PANIs after evaluating the packable and non-packable instructions. The Adaptive Code Fraction Reduction Method packs high fraction code by removing and/or hiding flow control instructions from the code and converts simplified reduced fraction code, which provides a fewer code fractions and a greater number of the native instructions between fractions than the input high fraction code found in prior arts.
The Adaptive Code Fraction Reduction Method provides a means for accurate advanced instruction prefetch and fetch by obtaining information earlier on how many instructions from which locations than the prior arts. The Adaptive Code Fraction Reduction Method generally generates two different types of code—PANI and NIPI from the software compiled program, such as the assembly program, after another round of compilation. The PANIs represent flow of instructions in simplified form. The NIPIs provide flow of native instructions of each packed instructions found in PANIs. The PANIs contain associative opcodes and/or other information, such as start and/or end locations of the native instruction segments of the packed normative instructions, the number of instructions packed in each packed normative instruction, and so on, for the Adaptive Code Fraction Reduction System Apparatus to distinguish different instructions from PANIs as well as to access the number of native instructions from the associative NIPIs.
The invented Adaptive Code Fraction Reduction System Apparatus adaptively fetches and/or prefetches a single or a plurality of PANIs concurrently while delivering a single or a plurality of the associative NIPIs fetched to a single or a plurality of microprocessors in its programming order. The Adaptive Code Fraction Reduction System Apparatus distinguishes the prefetched and fetched packed normative and non-packed native instructions from PANIs stored in the main instruction memory via a single or a plurality of levels of instruction cache memories before delivering the purely native instructions to a single or a plurality of microprocessors. The Adaptive Code Fraction Reduction System Apparatus also prefetches a single or a plurality of the next prospective PANIs while delivering the associative NIPIs and/or non-packed native instructions in PANIs to a single or a plurality of microprocessors.
The Adaptive Code Fraction Reduction Method and System Apparatus for Microprocessor System is designed for reducing instruction cache memory area and operating energy, enhancing access time, resolving or lightening the cost of instruction cache miss penalty, and improving the overall performance of the microprocessor system. The Adaptive Code Fraction Reduction Method and System Apparatus for Microprocessor System uses an Adaptive Code Fraction Reduction Method integrated with a concurrently accessible hierarchical memory system consisting of cache and main memories to achieve the same or similar effect of adaptive concurrent instruction fetching and prefetching of a single or a plurality of native instructions.
The Adaptive Code Fraction Reduction Method and System Apparatus for Microprocessor System permits considerably conserving instruction cache memory or simplifying the cache organization from the hierarchical instruction memory system. Additionally, the Adaptive Code Fraction Reduction Method and System Apparatus for Microprocessor System prefetches a single or a plurality of PANIs on the prospective locations in the program flow concurrently for enhancing cache hit rate and prefetches a single or a plurality of the associative NIPIs. Furthermore, the invention prevents the instruction cache memories from wasting energy by accurately prefetching and fetching the native instructions that are highly used once they have been accessed and stored in the instruction cache memories. Since more operations, including branches, subroutine callers, and subroutine returns, are reduced and/or packed into packed normative instructions, which are stored in and accessed from small, simple, and low-power consumed cache memories, such as direct mapped cache memories, the invention is useful for the low-power and performance-aware mobile microprocessor systems. Furthermore, software developers can compose their own compatible and ciphered instructions before runtime and prefetch and fetch purely native instructions concurrently from the main memory via a single or a plurality of levels of cache memories without worrying about code compatibility or modifying microprocessors.